Debug & Analysis

spv_debug

Integrated interactive debug platform for fast root-cause analysis in large-scale digital and analog designs

spv_debug - Interactive Debug Platform Signal Hierarchy + tb_top.u_dut + cpu_core - clk - rst_n - data_in[7:0] - data_out[7:0] + alu - op[3:0] - result[7:0] + uvm_test - seq_item Waveform Viewer clk _|~|_|~|_|~|_|~|_ rst_n ~~~|________________ data 00 XX A5 3C FF 2B valid ___|--|__|--|__|--- state IDLE RUN DONE ERR cursor ─── @ 45ns (delta 0) T=45ns Transaction Log [45ns] REQ addr=0xA5 data=0x3C [50ns] ACK status=OK latency=5 Source Browser 1 module cpu_core( 2 input clk, rst_n, 3 input [7:0] data_in, 4 output [7:0] data_out 5 ); 6 always @(posedge clk) begin 7 if (!rst_n) 8 data_out <= 8'b0; 9 else 10 data_out <= data_in; 11 end breakpoint

Waveform Viewer

High-performance waveform viewer with signal grouping, value filtering, and advanced display options.

Signal Tracing

Automatic signal tracing from source to sink with cross-probing between source code and waveforms.

Transaction Debug

Transaction-level debugging for UVM environments with protocol-aware viewing and analysis.

Debug Bookmarks

Save and recall debug states with hierarchical bookmarks and session management.

Source Browser

Integrated source code browser with syntax highlighting and automatic error navigation.

Cross-Platform Integration

Seamless integration with spv_sim, spv_formal, and industry-standard simulation formats.

spv_debug — Coming Soon

This product is under development. Contact us to join the early-access interest list.

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