Design IP

spv_core

High-performance RISC-V processor core with integrated AI/ML accelerators for edge inference

spv_core - RISC-V AI/ML Processor RISC-V RV64GC Core with AI/ML Accelerators ALU Integer/FP FPU FP16/BF16 ML Accel CNN/RNN/Transformer Vector Ext RVV 1.0 INT8/FP16 Cache L1/L2 64KB TCM Tightly Coupled AXI4 Bus Interface Power Mgmt DVFS / Clock Gating Debug JTAG / Trace Interrupt PLIC / CLINT Security TrustZone / PMP AI

RV64GC ISA

Full RISC-V 64-bit base integer, multiply/divide, atomic, and compressed extensions.

Vector Extensions

RVV 1.0 vector extensions with INT8/FP16/BF16 MAC operations for ML inference.

ML Accelerators

Dedicated neural network accelerator for convolution, pooling, and activation functions.

Memory System

Integrated L1/L2 cache with optional tightly-coupled memory for real-time applications.

Power Management

Advanced clock gating, power domains, and dynamic voltage scaling support.

Integration

RTL source with verification suite, FPGA bitstream, and software development kit.

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