Complete EDA Solutions
Verification, analysis, and implementation tools for modern silicon design.
Verification & Simulation
RTL simulation, waveform viewing, formal property verification, and coverage analysis
TraceSim
RTL Simulation Engine
High-performance Verilog/SystemVerilog simulation with mixed-signal support and UVM methodology integration.
- Mixed-Signal Simulation
- UVM Support
- Multi-Threaded
TraceWave
Waveform Viewer & Debug
High-performance waveform viewer for viewing, analyzing, and debugging simulation output with advanced signal analysis tools.
- Multi-Format VCD/FSDB
- Signal Search & Filter
- Analog Overlay
Verity Formal
Formal Verification
Complete formal property verification solution with SVA support, model checking, and formal equivalency.
- SVA Assertions
- Model Checking
- Equivalence Checking
Covera
Coverage Analysis
Comprehensive coverage analysis with statement, branch, toggle, FSM, and functional coverage metrics.
- Multi-Metric Coverage
- Coverage Holes
- Merge & Report
TraceDebug
Debug Analysis Tools
Advanced debug and trace analysis for post-silicon validation and system-level debugging.
- Trace Analysis
- Breakpoints
- Variable Watch
RTL Analysis
Automated code-quality, clock-domain, and reset-domain analysis.
Lucid Lint
Advanced Linting Tool
Sophisticated linting solution for RTL analysis and code quality enforcement with customizable policies.
- RTL Analysis
- Code Quality
- Design Rules
Guardian CDC
Clock Domain Crossing
Advanced CDC analysis tool with multi-bit crossing detection, synchronizer verification, and metastability analysis.
- Multi-Bit CDC Analysis
- Synchronizer Verification
- Metastability Analysis
Guardian RDC
Reset Domain Crossing
Sophisticated RDC analysis for async reset verification with recovery/removal timing and hierarchical analysis.
- Async Reset Verification
- Timing Analysis
- RDC Sign-Off
Timing & Power Analysis
Static timing analysis, power analysis, and constraint management for design sign-off
TimePath
Static Timing Analysis
High-performance STA with multi-mode multi-corner analysis and advanced on-chip variation support.
- Multi-Mode Multi-Corner
- OCV Analysis
- Timing Sign-Off
PowerScope
Power Analysis
Comprehensive power analysis with vector-based and vectorless modes for dynamic and static power analysis.
- Dynamic Power Analysis
- Leakage Analysis
- Power Sign-Off
Concorda
Constraint Management
Advanced constraint validation and management for SDC/UPF with formal-based verification.
- SDC Validation
- UPF Analysis
- Constraint Sign-Off
Design IPs
Reusable silicon-proven IP blocks for accelerated SoC development
SPNoC
Network on Chip Interconnect
Flexible, high-speed modular Network-on-Chip interconnect IP for complex SoC architectures with configurable topology.
- Configurable Topology
- QoS Support
- AXI/ACE Interface
SPCore
RISC-V AI/ML Processor
High-performance RISC-V processor core with integrated AI/ML accelerators for edge inference applications.
- RV64GC ISA
- Vector Extensions
- ML Accelerators
Emulation & Prototyping Coming Soon
FPGA-based emulation and rapid prototyping for pre-silicon validation
Celeris
FPGA Emulation & Prototyping
Multi-FPGA emulation platform for pre-silicon validation of complex SoC designs with real-time debug.
- Multi-FPGA Partitioning
- Real-Time Tracing
- iCE40 / ECP5 / Nexus
- Artix-7 / Spartan-7 / Gowin
- Cyclone V / NanoXplore
Physical Design Coming Soon
Next-generation tools for physical implementation
Fabrica
Physical Design Tools
Advanced physical design automation for floorplanning, placement, clock tree synthesis, and routing.
- Floorplanning
- Placement & CTS
- Routing
Design for Test Coming Soon
DFT insertion, test generation, and manufacturing test solutions
Apertis DFT
Design for Test
Comprehensive DFT insertion and verification tools for scan chains, BIST, and test point insertion.
- Scan Chain Insertion
- Test Point Insertion
- DFT Verification
Vectora
ATPG & MBIST
Advanced test pattern generation and memory built-in self-test for manufacturing test.
- Stuck-At & Transition
- Memory BIST
- Fault Coverage