TraceSim
RTL Simulation Engine
Event-driven multi-threaded simulator for large digital and mixed-signal designs with UVM support.
- Mixed-Signal
- UVM
- Multi-Threaded
Verification & Simulation
Simulate, view, prove, cover, and debug RTL at scale.
TraceWave
Waveform Viewer
High-performance waveform viewing and debug for simulation results at SoC scale.
- Fast Load
- Hierarchy
- Debug Cursors
Verity Formal
Formal Verification
Exhaustive property checking and formal sign-off for critical RTL blocks.
- Properties
- Assertions
- Sign-Off
Covera
Coverage Analysis
Code and functional coverage with hole analysis, merge, and reporting.
- Multi-Metric
- Hole Analysis
- Merge & Report
TraceDebug
Debug Platform
Interactive debug and trace analysis for complex SoC bring-up.
- Trace Analysis
- Breakpoints
- Watchpoints
RTL Analysis
Lint, clock-domain, and reset-domain correctness before silicon.
Lucid Lint
RTL Linting
Design-quality checks that catch structural and coding issues early.
- Style Rules
- Structural
- Custom Rulesets
Guardian CDC
Clock Domain Crossing
Multi-bit CDC analysis, synchronizer verification, and metastability insight.
- Multi-Bit CDC
- Synchronizers
- MTBF Analysis
Guardian RDC
Reset Domain Crossing
Async reset verification with recovery/removal and hierarchical analysis.
- Async Reset
- Timing Checks
- RDC Sign-Off
Timing & Power
Close timing and power with sign-off grade analysis.
TimePath
Static Timing
Path-based STA for digital timing closure and sign-off.
- Path Analysis
- Multi-Corner
- Constraints
PowerScope
Power Analysis
Dynamic and static power estimation with vector and vectorless modes.
- Dynamic Power
- Leakage
- Power Sign-Off
Concorda
Constraint Management
SDC/UPF validation and constraint sign-off across the implementation flow.
- SDC Validation
- UPF Analysis
- Constraint Sign-Off
Design IPs
Production-ready interconnect and processor IP with verification support.
SPNoC
Network-on-Chip
Scalable NoC interconnect IP for multi-core SoC designs.
- Topology
- QoS
- Verification Kit
SPCore
RISC-V Core IP
High-performance RISC-V core with AI/ML accelerator support.
- RV64GC
- ML Accel
- Vector Ext
Celeris
FPGA Emulation
Multi-FPGA emulation and prototyping for pre-silicon validation.
- Partitioning
- Real-Time Trace
- Multi-Vendor FPGA
Physical Design & DFT
Implementation and manufacturing test — open for early interest.
Fabrica
Physical Design
Floorplanning, placement, CTS, and routing automation.
- Floorplan
- Place & CTS
- Route
Apertis DFT
Design for Test
Scan insertion, test points, and DFT structural verification.
- Scan Insert
- Test Points
- DFT DRC
Vectora
ATPG & MBIST
Pattern generation and memory BIST for high manufacturing coverage.
- Stuck-At / Transition
- Memory BIST
- ATE Export